Volume 2 Issue 1

Design of carry save adder using transmission gate logic (140051)

DOI :

Abstract : In this paper Carry Save Adder has been implemente d. The comparison is done on the basis of two perfo rmances such as area,power consumption. The full adder cells fo r low power applications have been implemented usin g transmission gate based technique for sum and carry operation. I n this paper transmission gate also used. It used t o minimize the transistor count. By using the transmission gate th e transistor count has decreased thereby the total chip area gets minimized and the power consumption also gets reduc ed.

Pages :

Downloads : 1681

Publication Date :

Modified Date : 2020-11-21

Cite/Export :

J.Princy Joice , M.Anitha , Mrs.I.Rexlin Sheeba , "Design of carry save adder using transmission gate logic", IJIERT - International Journal of Innovations in Engineering Research and Technology, Volume 2 Issue 1, ISSN : 2394-3696, Page No.