Volume 3 Issue 1



Abstract : Security of the data is most important aspect in communication. In global world security of data is very common parameter . There is need for secure transaction in networking,communication,commerce,and secure messaging has moved encryption into the commercial area. Advanced encryption standard (AES) was issued as Federal Information Processing Standards (FIPS) by National Institute of Standards and Technology (NIST) as a successor to data encryption standard (DES) algorithms. The high level of security and the fast hardware and software implementations of the Advanced Encryption Standard (AES) have made i t the first choice for many critical applications. For secure data transmissions in wireless military communication and mobile telephony requires encryption with limited area constraints. Therefore,the current work will be focuses on designing and simulat ing low area AES encryption module and calculate power. Advanced Encryption Standard is a symmetric key block cipher encryption algorithm. Understanding the need proposed work introduces the design and simulation of the block cipher 128 bit Advanced Encryp tion Standard (AES - 12 8) with low area constraint. I propose low area design by reduction of area occupancy which will be offered .

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Modified Date : 2016-01-20

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Assi. Prof. Sarika N. Wagaj , Assi. Prof. Preeti Kadam , Assoc. Prof Sajid Shaikh , "ADVANCED ENCRYPTION STANDARD WITH LOW AREA & POWER ON FPGA MODULE", IJIERT - International Journal of Innovations in Engineering Research and Technology, Volume 3 Issue 1, ISSN : 2394-3696, Page No.